A Pipelined Multi-core MIPS Machine Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul PDF

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

ISBN-10: 3319139053

ISBN-13: 9783319139050

This monograph relies at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland college, Germany. It incorporates a gate point building of a multi-core computing device with pipelined MIPS processor cores and a sequentially constant shared memory.

The ebook comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence. This opens how to the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and hence deterministic. against this the reference versions opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness evidence of the shared reminiscence on the gate point are the most technical contributions of this work.

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Extra resources for A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof

Example text

For the first of de Morgan’s laws this is illustrated in Table 4. 2 Solving Equations We consider expressions e and ei (where 1 ≤ i ≤ n), involving a vector of variables x. We derive three basic lemmas about the solution of Boolean equations. For a ∈ B we define ea = Inspection of the semantics of solving negation. e e a=1 a=0. 17 (solving negation). Given a Boolean expression e(x) and a ∈ B, we have ea = 1 ↔ e = a . Inspection of the semantics of ∧ in Table 3 gives (e1 ∧ e2 ) = 1 ↔ e1 = 1 ∧ e2 = 1 .

N-bit multiplexer x xn−1 n x0 1 1 ··· n 1 yn−1 y (a) symbol 1 y0 (b) implementation Fig. 9. n-bit inverter inputs and outputs satisfy z[n − 1 : 0] = x[n − 1 : 0] ◦ y[n − 1 : 0] u[n − 1 : 0] = v ◦ y[n − 1 : 0] . n-bit ◦-gates are simply realized in the first case by n separate ◦-gates as shown in Fig. 10(b). In the second case all left inputs of the gates are connected to the same input v. An n-bit ◦-tree has inputs a[n − 1 : 0] and a single output b satisfying b = ◦ni=1 ai . 36 3 Hardware x xn−1 y n 1 n v 1 z0 yn−1 1 n v 1 ◦ 1 un−1 (a) symbol 1 ··· 1 n y0 1 ◦ ◦ u ◦ ··· zn−1 y 1 1 1 n y0 1 ◦ v x0 1 ◦ z yn−1 u0 (b) implementation Fig.

For the definition of the value y(t) of gates g at time t in the detailed model, we distinguish three cases (see Fig. 22): • Regular signal propagation. Here, all input signals are binary and stable for the maximal propagation delay β before t. For inverters y this is captured by the following predicate: reg(y, t) ↔ ∃a ∈ B : ∀t ∈ [t − β, t] : in1(y)(t ) = a . Gate y in this case outputs a at time t. For ◦-gates y we define reg(y, t) ↔ ∃a, b ∈ B : ∀t ∈ [t − β, t] : in1(y)(t ) = a ∧ in2(y)(t ) = b .

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A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul


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