By Himanshu Bhatnagar
Complex ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment variation describes the complex suggestions and strategies used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the total ASIC layout stream technique certain for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this ebook is on real-time program of Synopsys instruments, used to wrestle quite a few difficulties obvious at VDSM geometries. Readers could be uncovered to a good layout technique for dealing with advanced, sub-micron ASIC designs. value is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to structure, actual synthesis, and static timing research. At each one step, difficulties concerning every one section of the layout move are pointed out, with suggestions and work-around defined intimately. additionally, an important concerns regarding structure, together with clock tree synthesis and back-end integration (links to structure) also are mentioned at size. in addition, the e-book comprises in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding types, exact in the direction of optimum synthesis answer. aim audiences for this publication are working towards ASIC layout engineers and masters point scholars venture complicated VLSI classes on ASIC chip layout and DFT suggestions.
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Extra info for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
The timing driven placement method forces the layout tool to place the cells according to the criticality of the timing between the cells. After the placement of cells, the clock tree is inserted in the design by the layout tool. The clock tree insertion is optional and depends solely on the design and user’s preference. Users may opt to use more traditional methods of routing the clock network, for example, using fishbone/spine structure for the clocks in order to reduce the total delay and skew of the clock.
12. Post-layout static timing analysis using PrimeTime. 13. Functional gate-level simulation of the design with post-layout timing (if desired). 14. Tape out after LVS and DRC verification. 1 Chapter 1 Physical Synthesis Traditionally synthesis methods are based on using the wire-load models. The basic nature of the wire-load models is such that they are fanout based. In other words, the delay computation of cells is performed based on the number of fanouts a cell drives. 35um), it is not suitable for smaller geometries.
The estimated delays are back annotated to PrimeTime for analysis, and only when the timing is considered satisfactory, the remaining process is allowed to proceed. Detailed routing is the final step that is performed by the layout tool. After detailed route is complete, the real timing delays of the chip are extracted, and plugged into PrimeTime for analysis. These steps are iterative and depend on the timing margins of the design. If the design fails timing requirements, post-layout optimization is performed on the design before undergoing another iteration of layout.
Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime by Himanshu Bhatnagar