By Norman G. Einspruch
Includes contributions from a dozen execs from the inner most zone and academia. Discusses numerous machine physics subject matters of specific curiosity to and collage researchers in electric engineering, laptop technology, and digital fabrics. Emphasizes actual description, mode
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6. Lifetimes of various L D D structures. Lifetime is defined by a 10% degradation in linear transconductance. Gate length is 1 jxm in all cases, (a) L D D dose is 2 X 1 0 C I T T , minimum reoxidation in dry 0 . (b) L D D dose is 1 x 1 0 c m , reoxidation in wet 0 , with additional drive-in. (c) L D D dose is 1 x 1 0 c m , reoxidation in wet 0 , without additional drive-in. (From Huang et al. ) 1 3 13 2 - 2 2 2 13 - 2 2 In the submicron range, standard L D D devices are unlikely to be adequate for 5-V operation.
One aspect that will not be considered further, however, is that of multilevel metallization. Most modern M O S technologies use at least two metal interconnect levels. Conceptually, this is quite simple, involving the deposition an addition dielectric layer, 15 3 A + 44 Alan G. Lewis and John Y. Chen silicon n i t r i d e Fig. 1. Basic four-mask N M O S process, (a) Definition of nitride/oxide islands over active area (mask 1). (b) LOCOS field oxidation, (c) Gate oxidation and channel implants, (d) Gate definition (mask 2) and source/drain implant, (e) Oxide deposition and contact definition and etch (mask 3 ) .
12. 13. 14. 15. 16. 17. 18. D. Kahng and M. M. " D R C , Pittsburgh, Pennsylvania, 1960. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, Design of ion-implanted MOSFETs with very small physical dimensions. IEEE J. SolidState Circuits SC-9, 256-268 (1974). P. K. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, The impact of scaling laws on the choice of ^-channel and p-channel for MOS VLSI. IEEE Electron Device Lett EDL-1, 220-223 (1980). G. Baccarani, M.
Advanced MOS Device Physics by Norman G. Einspruch